1. Field of the Invention
This invention generally relates to a system and method for transferring data between two relatively autonomous processors, one on each side of the data transfer operation.
2. Description of the Related Art
When two nodes on a network need to exchange data over a network, current methods often require that the nodes expose their address spaces to each other. For instance, in a direct memory access (“DMA”) operation, the DMA engine needs to know the memory addresses of where to retrieve the data and where to place the data. This presents not only a security problem if a node wants to keep its address space private, but also requires that at least one of the systems have intimate knowledge about the hardware of the other system.
Moreover, transferring data between nodes often requires close synchronization of hardware resources on both ends of the transfer during the data transfer—for instance, between the DMA engine, a hard drive controller and memory. In some cases, the source node often needs to wait for the destination node to be free before the data transfer can begin. Such synchronization permits the nodes to ensure that all the data is transferred in an orderly fashion, but ties up the system while the data transfer is taking place.
Another type of well-know data transfer methodology currently in use today is Internet Protocol (“IP”). This protocol is designed for packet-switched computer communications networks. In this protocol, data is transferred in blocks called “datagrams” from a source to a destination. Each source and destination has an fixed-length address. The datagrams are routed through various processor, such as routers, and each processor would determine where to next send the datagram. There is no hardware synchronization per se.
It would be desirable to overcome these limitations as well as the need for systems/nodes to have intimate knowledge of other systems that they are communicating with in order to transfer data.